/******************************************************************************
*
* MODULE:    Leds_TB.v
* DEVICE:     Test Bench
* PROJECT:   Tarea 2 Diseño Electronico Digital
* AUTHOR:    Ricardo Dávila Castro   
* DATE:      2010 19:35:08
*
* ABSTRACT:  Testbench leds Ejercicio 1
*            
*******************************************************************************/
`timescale 1ns / 100ps

`ifndef 	LEDS_TB
`define    LEDS_TB


module Leds_TB ;

reg clk_50M;
reg [3:0]SW;
reg Captura;
reg RST;
wire [7:0]LED;

initial 
	begin
		clk_50M = 1'b0;
		forever #1 clk_50M =~clk_50M;
	end

initial 
	begin
		RST = 1'b1;
		Captura = 1'b0;
		SW = 4'b1010;
		#2 RST = ~RST;
		#5 Captura = ~ Captura;
		#40 Captura = ~ Captura;
		#20 Captura = ~Captura;
		//#20 Captura = ~Captura;
		SW = 4'b1111;
		#15 Captura = ~Captura;
		#40 Captura = ~Captura;
		SW = 4'b1001;
		#500 Captura = ~Captura;
	end
Leds Leds_inst(.CLK(clk_50M),.RST(RST),.SW(SW),.pshB_Captura(Captura),.LED(LED));

endmodule
`endif